1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the semiconductor device, and more particularly to a 3D non-volatile memory device including a pipe gate and a method of manufacturing the 3D non-volatile memory device.
2. Description of the Related Art
A non-volatile memory device is a memory device in which stored data is maintained even if power supply is interrupted. As the integration of memory devices having a 2-dimensional structure in which a single layer memory device is formed on a silicon substrate reaches a limit, a 3-Dimensional (3D) non-volatile memory device in which memory cells are vertically stacked on a silicon substrate has been suggested.
Hereinafter, a structure of the 3D non-volatile memory device in the related art and problems associated with the 3D non-volatile memory device will be described in detail with reference to the drawing.
FIG. 1 is a perspective view illustrating a structure of the 3D non-volatile memory device in the related art. For ease of description, interlayer insulating layers are omitted in the drawing.
As illustrated in FIG. 1, the 3D non-volatile memory device in the related art includes a channel layer CH including a pipe channel layer P_CH buried in a pipe gate PG and a pair of vertical channel layers V_CH connected with the pipe channel layer P_CH. Further, the memory device includes word lines WL stacked while surrounding the vertical channel layers V_CH, and a source selection line SSL and a drain selection line DSL stacked on the word lines WL. Strings adjacent in a second direction II-II′ (of a first I-I′ and second II-II′ direction) are commonly connected to one source line SL, and the strings included in a string row extended in the second direction II-II′ are commonly connected to one bit line BL.
Here, the channel layer CH is enclosed by a memory layer (not shown). The memory layer includes a tunnel insulating layer, a charge trap layer, and a charge blocking layer. Further, the pipe gate PG is formed of a poly silicon layer including an N-type of impurity.
However, since the N-type poly silicon layer is formed of a material having a small work function, a problem may occur in that charge trapped in a gate insulating layer of a pipe transistor in an erase operation is generated. Especially, because of charge trapped in the charge trap layer among the gate insulating layers, a threshold voltage of the pipe transistor is increased, and thus a cell current is decreased, thereby causing a deterioration of a characteristic of the memory device.